In analog circuit design, process variations both on-die and between wafer runs can have many deleterious effects. Problems resulting from these variations include unpredictable bias conditions, variations in target bandwidth and skew, functionality issues and reduction in yield. The variations are expected to worsen in deep sub-micron technologies due to difficulties in printing and uniformly doping nanometer-scale geometries. Robust circuit design with performance tolerant to these variations is a tremendous challenge.